First and second conventional level conversion circuits are described on pages 184 and 185 of ISSCC DIG., Feb. 1989, respectively.
Both of the first and second conventional level conversion circuits comprise an input buffer circuit and a cascade current mirror circuit, respectively.
In the first conventional level conversion circuit, the input buffer circuit comprises four NPN bipolar transistors, three constant current sources, etc. to provide a current switch and two emitter-follower circuits, and the cascade current mirror circuit comprises two P channel MOSFETs and two N channel MOSFETs. Later, the detail of the circuit structure will be explained.
In operation, when a high level input signal of the ECL level is applied to an input terminal connected a base of the NPN bipolar transistor of the current switch in the input buffer circuit, a low level output signal of the CMOS level is from an output terminal connected to a common drain of the P and N channel MOSFETs in the cascade current mirror circuit. Later, the detail of this operation will be explained.
In the second conventional level conversion circuit, the input buffer circuit comprises three NPN bipolar transistors, two constant current sources to provide a current switch and an emitter-follower circuit, and the cascade current mirror circuit comprises two P channel MOSFETs and two N channel MOSFETs, although the circuit structure is slightly different from that of the first conventional level conversion circuit, as also will be explained later.
In operation, a high level input signal of the ECL level is converted to a high level output signal of the CMOS level in this second conventional level conversion circuit as different from the level conversion of the first conventional level conversion circuit. Later, the detail of this operation will be also explained.
However, the first conventional level conversion circuit has a disadvantage in that a rise time of an output signal of the CMOS level is delayed. This disadvantage is caused by the following reason. That is, it is necessary that the transistors of the current switch are not saturated in the input buffer circuit to provide a high speed level conversion operation. For this purpose, an amplitude of an output signal supplied from the input buffer circuit can be approximately 1.2 V at the highest level, so that the output signal of the input buffer circuit will be "V.sub.cc -V.sub.f " as positive, and "V.sub.cc -V.sub.f -1.2 V" as complementary, where V.sub.cc is a power supply voltage of the input buffer circuit, and V.sub.f is a forward ON voltage between emitter and base of the transistors of the emitter-follower circuits. As a result, a voltage of "1.2 V+V.sub.f -V.sub.t " is applied across source and gate of the P channel MOSFET on the ON side of the cascade current mirror circuit, where V.sub.t is a threshold voltage of the MOSFET. Consequently, a voltage of approximately 1.2 V is only applied across the gate and source of the P channel MOSFET on the output side of the cascade current mirror circuit at the highest level, so that a current flowing through the output side P channel MOSFET can not be larger than a certain level to result in the aformentioned disadvantage.
Further, the second conventional level conversion circuit has disadvantages in that a fall time of an output signal of the CMOS level is delayed, and a low level of the output signal is floated above a predetermined level to result in the difficulty that a gate voltage of the P channel MOSFET on the output side of the cascade current mirror circuit is not properly set. These disadvantages are caused by the following reason. That is, an ON current flowing through the P channel MOSFET on the output side of the cascade current mirror circuit can be large in the decrease of a gate voltage applied thereto under the condition that an amplitude of an output signal of the input buffer circuit is not increased. On the contrary, when the gate voltage is decreased, a large current flows therethrough to result in the aforementioned disadvantages, even if the P channel MOSFET is turned off.
The second conventional level conversion circuit has an additional disadvantage in that an adequate gate voltage applied to the P channel MOSFET on the output side of the cascade current mirror circuit is fluctuated due to the fluctuation of an output voltage of the input buffer circuit which is caused by the dispersion of manufacturing condition, the deviation of a power supply voltage, etc.